1. Field
Exemplary embodiments of the present invention relate to a phase difference quantization circuit for quantizing a phase difference between two signals into digital codes, a delay value control circuit of the phase difference quantization circuit, and a delay circuit capable of calibrating a delay value.
2. Description of the Related Art
A phase difference quantization circuit is a circuit which generates digital codes corresponding to a phase difference between two signals with different phases.
FIG. 1 is a diagram showing a conventional phase difference quantization circuit.
FIG. 1 illustrates a phase difference quantization circuit which includes four phase comparison units 150, 250, 350 and 450 and three delay units 100, 200 and 300.
The first phase comparison unit 150 is configured to compare the phases of the signal loaded on a first first-node AD1 and the signal loaded on a first second-node AD2, generate a first up/down signal Q<4> and transfer the generated first up/down signal Q<4> to the first delay unit 100.
The first delay unit 100 is configured to transfer the signal loaded on the first first-node AD1 to a second first-node BD1 and the signal loaded on the first second-node AD2 to a second second-node BD2. At this time, the first delay unit 100 selects any one of the signal loaded on the first first-node AD1 and the signal loaded on the first second-node AD2 in response to the first up/down signal Q<∝>, delays the selected signal by a first delay value, and transfers the delayed signal.
The second phase comparison unit 250 is configured to compare the phases of the signal loaded on the second first-node BD1 and the signal loaded on the second second-node BD2, generate a second up/down signal Q<3> and transfer the generated second up/down signal Q<3> to the second delay unit 200.
The second delay unit 200 is configured to transfer the signal loaded on the second first-node BD1 to a third first-node CD1 and the signal loaded on the second second-node BD2 to a third second-node CD2. At this time, the second delay unit 200 selects any one of the signal loaded on the second first-node BD1 and the signal loaded on the second second-node BD2 in response to the second up/down signal Q<3>, delays the selected signal by a second delay value, and transfers the delayed signal.
The third phase comparison unit 350 is configured to compare the phases of the signal loaded on the third first-node CD1 and the signal loaded on the third second-node CD2, generate a third up/down signal Q<2> and transfer the generated third up/down signal Q<2> to the third delay unit 300.
The third delay unit 300 is configured to transfer the signal loaded on the third first-node CD1 to a fourth first-node DD1 and the signal loaded on the third second-node CD2 to a fourth second-node DD2. At this time, the third delay unit 300 selects any one of the signal loaded on the third first-node CD1 and the signal loaded on the third second-node CD2 in response to the third up/down signal Q<2>, delays the selected signal by a third delay value, and transfers the delayed signal.
The fourth phase comparison unit 450 is configured to compare the phases of the signal loaded on the fourth first-node DD1 and the signal loaded on the fourth second-node DD2 and generate a fourth up/down signal Q<1>.
FIG. 2 is a timing diagram showing operations of the conventional phase difference quantization circuit shown in FIG. 1. For illustration purposes, it is assumed that the first delay value of the first delay unit 100 is 40 ps (picoseconds), the second delay value of the second delay unit 200 is 20 ps, and the third delay value of the third delay unit 300 is 10 ps. Furthermore, it is assumed that the phase of a first input signal IN1 is earlier than the phase of a second input signal IN2 by 65 ps. The first input signal IN1 and the second input signal IN2 with difference phases are inputted to the first phase comparison unit 150 through the first first-node AD1 and the first second-node AD2, respectively. Since the phase of the signal loaded on the first first-node AD1 (that is, the first input signal IN1) is earlier than the phase of the signal loaded on the first second-node AD2 (that is, the second input signal IN2), the first phase comparison unit 150 outputs the first up/down signal Q<4> of a high level to the first delay unit 100. The first delay unit 100 is inputted with the signal loaded on the first first-node AD1 and the signal loaded on the first second-node AD2, delays the signal loaded on the first first-node AD1 by 40 ps in response to the first up/down signal Q<4> of the high level, transfers the delayed signal to the second first-node BD1, and transfers the signal loaded on the first second-node AD2 to the second second-node BD2 as is without further delaying the signal.
The second phase comparison unit 250 compares the phases of the signals loaded on the second first-node BD1 and the second second-node BD2. Since the phase of the signal loaded on the second first-node BD1 is earlier by 25 ps than the phase of the signal loaded on the second second-node BD2, the second phase comparison unit 250 outputs the second up/down signal Q<3> of a high level to the second delay unit 200. The second delay unit 200 is inputted with the signals loaded on the second first-node BD1 and the second second-node BD2, delays the signal loaded on the second first-node BD1 by 20 ps in response to the second up/down signal Q<3> of the high level, transfers the delayed signal to the third first-node CD1, and transfers the signal loaded on the second second-node BD2 to the third second-node CD2 as is without further delaying the signal.
The third phase comparison unit 350 compares the phases of the signals loaded on the third first-node CD1 and the third second-node CD2. Since the phase of the signal loaded on the third first-node CD1 is earlier by 5 ps than the phase of the signal loaded on the third second-node CD2, the third phase comparison unit 350 outputs the third up/down signal Q<2> of a high level to the third delay unit 300. The third delay unit 300 is inputted with the signals loaded on the third first-node CD1 and the third second-node CD2, delays the signal loaded on the third first-node CD1 by 10 ps in response to the third up/down signal Q<2> of the high level, transfers the delayed signal to the fourth first-node DD1, and transfers the signal loaded on the third second-node CD2 to the fourth second-node DD2 as is without further delaying the signal.
The fourth phase comparison unit 450 compares the phases of the signals loaded on the fourth first-node DD1 and the fourth second-node DD2. Since the phase of the signal loaded on the fourth second-node DD2 is earlier by 5 ps than the phase of the signal loaded on the fourth first-node DD1, the fourth phase comparison unit 450 outputs the fourth up/down signal Q<1> of a low level.
As a consequence, binary codes that represent the phase difference between the first input signal IN1 and the second input signal IN2 are acquired as 1110 by combining the first to fourth up/down signals Q<4:1>. The fourth bit Q<4> indicates that the phase of which signal of the input signals IN1 and IN2 is earlier. Since the fourth bit is 1, it is meant that the phase of the first input signal IN1 is earlier than the phase of the second input signal IN2. The remaining three bits indicate an actual phase difference between the signals IN1 and IN2. That is to say, it can be seen that the phase difference between the signals IN1 and IN2 is larger than 1*40 ps+1*20 ps and is smaller than 1*40 ps+1*20 ps+1*10 ps.
The delay values of the delay units 100, 200 and 300 constituting the phase difference quantization circuit generally have a constant ratio (2:1). In other words, the delay value 40 ps of the first delay unit 100 and the delay value 20 ps of the second delay unit 200 have the ratio of 2:1, and the delay value 20 ps of the second delay unit 200 and the delay value 10 ps of the third delay unit 300 have the ratio of 2:1.
However, the delay values of the delay units 100, 200 and 300 constituting the phase difference quantization circuit are likely to change due to a variation in PVT (process, voltage and temperature). If the delay values of the delay units 100, 200 and 300 change, the delay value ratio between the delay units 100, 200 and 300 may deviate. If the delay value ratio between the delay units 100, 200 and 300 deviates, binary codes which precisely reflect the phase difference between two signals may not be generated.